Datasheet

Section 16 I
2
C Bus Interface (IIC) (Optional)
Rev. 3.00 Mar 21, 2006 page 414 of 788
REJ09B0300-0300
 Address match: When any slave address matches or the general call address is received in
slave receive mode with I
2
C bus format (including address reception after loss of master
arbitration)
 Start condition detection (in master mode)
 Stop condition detection (in slave mode)
• Selection of 16 internal clocks (in master mode)
• Direct bus drive (SCL/SDA pin)
 Four pins—P52/SCL0, P97/SDA0, P86/SCL1, and P42/SDA1 —(normally NMOS push-
pull outputs) function as NMOS open-drain outputs when the bus drive function is selected.
• Automatic switching from formatless mode to I
2
C bus format (IIC_0 only)
 Formatless operation (no start/stop conditions, non-addressing mode) in slave mode
 Operation using a common data pin (SDA) and independent clock pins (VSYNCI, SCL)
 Automatic switching from formatless mode to I
2
C bus format on the fall of the SCL pin