Datasheet

Rev. 3.00 Mar 21, 2006 page xlii of liv
Figure 14.5 Output Timing of RESO signal............................................................................ 355
Figure 14.6 Writing to TCNT and TCSR (WDT_0) ............................................................... 356
Figure 14.7 Conflict between TCNT Write and Increment..................................................... 357
Figure 14.8 Sample Circuit for Resetting System by RESO Signal........................................ 358
Section 15 Serial Communication Interface (SCI and IrDA)
Figure 15.1 Block Diagram of SCI ......................................................................................... 360
Figure 15.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits) .............................................. 376
Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode..................................... 378
Figure 15.4 Relation between Output Clock and Transmit Data Phase
(Asynchronous Mode) ......................................................................................... 379
Figure 15.5 Sample SCI Initialization Flowchart.................................................................... 380
Figure 15.6 Example of SCI Transmit Operation in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)................................................. 381
Figure 15.7 Sample Serial Transmission Flowchart................................................................ 382
Figure 15.8 Example of SCI Receive Operation in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)................................................. 383
Figure 15.9 Sample Serial Reception Flowchart (1) ............................................................... 385
Figure 15.9 Sample Serial Reception Flowchart (2) ............................................................... 386
Figure 15.10 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)......................................... 388
Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart....................................... 389
Figure 15.12 Example of SCI Receive Operation (Example with 8-Bit Data,
Multiprocessor Bit, One Stop Bit) ....................................................................... 390
Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1) ...................................... 391
Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2) ...................................... 392
Figure 15.14 Data Format in Clocked Synchronous Communication (LSB-First) ................... 393
Figure 15.15 Sample SCI Initialization Flowchart.................................................................... 394
Figure 15.16 Example of SCI Transmit Operation in Clocked Synchronous Mode ................. 396
Figure 15.17 Sample Serial Transmission Flowchart................................................................ 397
Figure 15.18 Example of SCI Receive Operation in Clocked Synchronous Mode................... 398
Figure 15.19 Sample Serial Reception Flowchart..................................................................... 399
Figure 15.20 Sample Flowchart of Simultaneous Serial Transmission and Reception............. 401
Figure 15.21 IrDA Block Diagram............................................................................................ 402
Figure 15.22 IrDA Transmission and Reception....................................................................... 403
Figure 15.23 Example of Transmission Using DTC in Clocked Synchronous Mode............... 407
Figure 15.24 Sample Flowchart for Mode Transition during Transmission ............................. 408
Figure 15.25 Pin States during Transmission in Asynchronous Mode (Internal Clock)........... 409
Figure 15.26 Pin States during Transmission in Clocked Synchronous Mode
(Internal Clock).................................................................................................... 409