Datasheet

Section 15 Serial Communication Interface (SCI and IrDA)
Rev. 3.00 Mar 21, 2006 page 360 of 788
REJ09B0300-0300
Clocked Synchronous Mode:
• Data length: 8 bits
• Receive error detection: Overrun errors
• Serial data communication with other LSIs that have the clock synchronized communication
function
A block diagram of the SCI is shown in figure 15.1.
RxD
TxD
SCK
Clock
φ
φ/4
φ/16
φ/64
TEI
TXI
RXI
ERI
SCMR
SSR
SCR
SMR
Transmission/
reception control
Baud rate
generator
BRR
Module data bus
RDR
TSRRSR
Parity generation
Parity check
Legend:
RSR : Receive shift register
RDR : Receive data register
TSR : Transmit shift register
TDR : Transmit data register
SMR : Serial mode register
TDR
Bus interface
Internal data bus
External clock
SCR : Serial control register
SSR : Serial status register
SCMR : Serial interface mode register
BRR : Bit rate register
Figure 15.1 Block Diagram of SCI