Datasheet

Rev. 3.00 Mar 21, 2006 page xxxix of liv
Figure 4.3 Operation when SP Value Is Odd ........................................................................ 87
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller ................................................................ 90
Figure 5.2 Relationship between Interrupts IRQ7 and IRQ6, Interrupts KIN15 to KIN0,
Interrupts WUE7 to WUE0, and Registers KMIMR, KMIMRA,
and WUEMRB..................................................................................................... 99
Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0 ........................................................ 101
Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control
Mode 0................................................................................................................. 106
Figure 5.5 State Transition in Interrupt Control Mode 1....................................................... 107
Figure 5.6 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control
Mode 1................................................................................................................. 109
Figure 5.7 Interrupt Exception Handling............................................................................... 111
Figure 5.8 DTC and Interrupt Controller .............................................................................. 113
Figure 5.9 Address Break Block Diagram ............................................................................ 115
Figure 5.10 Address Break Timing Example.......................................................................... 117
Figure 5.11 Conflict between Interrupt Generation and Disabling ......................................... 118
Section 6 Bus Controller (BSC)
Figure 6.1 Block Diagram of Bus Controller........................................................................ 122
Figure 6.2 IOS Signal Output Timing................................................................................... 128
Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space)........................ 129
Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space)....................... 130
Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space........................................................ 131
Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space........................................................ 132
Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access) ..................... 133
Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access)....................... 134
Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access)............................. 135
Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access) ..................... 136
Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access)....................... 137
Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access)............................. 138
Figure 6.13 Example of Wait State Insertion Timing (Pin Wait Mode).................................. 140
Figure 6.14 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1) ................ 141
Figure 6.15 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0) ................ 142
Figure 6.16 Examples of Idle Cycle Operation....................................................................... 143
Section 7 Data Transfer Controller (DTC)
Figure 7.1 Block Diagram of DTC........................................................................................ 146
Figure 7.2 Block Diagram of DTC Activation Source Control............................................. 152
Figure 7.3 DTC Register Information Location in Address Space........................................ 153