Datasheet

Section 14 Watchdog Timer (WDT)
Rev. 3.00 Mar 21, 2006 page 350 of 788
REJ09B0300-0300
• TCSR_1
Bit Bit Name Initial Value R/W Description
7OVF0
R/(W)
*
1
Overflow Flag
Indicates that TCNT has overflowed (changes from H'FF
to H'00).
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
However, when internal reset request generation is
selected in watchdog timer mode, OVF is cleared
automatically by the internal reset.
[Clearing conditions]
• When TCSR is read when OVF = 1
*
2
, then 0 is
written to OVF
• When 0 is written to TME
6WT/IT 0 R/W Timer Mode Select
Selects whether the WDT is used as a watchdog timer or
interval timer.
0: Interval timer mode
1: Watchdog timer mode
5 TME 0 R/W Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and is
initialized to H'00.
4 PSS 0 R/W Prescaler Select
Selects the clock source to be input to TCNT.
0: Counts the divided cycle of φ–based prescaler (PSM)
1: Counts the divided cycle of φSUB–based prescaler
(PSS)
3RST/NMI 0 R/W Reset or NMI
Selects to request an internal reset or an NMI interrupt
when TCNT has overflowed.
0: An NMI interrupt is requested
1: An internal reset is requested