Datasheet

Section 14 Watchdog Timer (WDT)
Rev. 3.00 Mar 21, 2006 page 347 of 788
REJ09B0300-0300
14.2 Input/Output Pins
The WDT has the pins listed in table 14.1.
Table 14.1 Pin Configuration
Name Symbol I/O Function
Reset output pin RESO Output Outputs the counter overflow signal in
watchdog timer mode
External sub-clock input
pin
EXCL Input Inputs the clock pulses to the WDT_1
prescaler counter
14.3 Register Descriptions
The WDT has the following registers. To prevent accidental overwriting, TCSR and TCNT have
to be written to in a method different from normal registers. For details, refer to section 14.6.1,
Notes on Register Access. For details on the system control register, refer to section 3.2.2, System
Control Register (SYSCR).
• Timer counter (TCNT)
• Timer control/status register (TCSR)
14.3.1 Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter.
TCNT is initialized to H'00 when the TME bit in the timer control/status register (TCSR) is
cleared to 0.