Datasheet

Section 13 Timer Connection
Rev. 3.00 Mar 21, 2006 page 327 of 788
REJ09B0300-0300
13.3.4 Edge Sense Register (SEDGR)
SEDGR detects a rising edge on the timer connection input pins and the occurrence of 2fH
modification, and determines the phase of the IVI and IHI signals.
Bit Bit Name Initial Value R/W Description
7 VEDG 0 R/(W)
*
1
VSYNCI Edge
Detects a rising edge on the VSYNCI pin.
[Clearing condition]
When 0 is written in VEDG after reading VEDG = 1
[Setting condition]
When a rising edge is detected on the VSYNCI pin
6HEDG 0 R/(W)
*
1
HSYNCI Edge
Detects a rising edge on the HSYNCI pin.
[Clearing condition]
When 0 is written in HEDG after reading HEDG = 1
[Setting condition]
When a rising edge is detected on the HSYNCI pin
5CEDG 0 R/(W)
*
1
CSYNCI Edge
Detects a rising edge on the CSYNCI pin.
[Clearing condition]
When 0 is written in CEDG after reading CEDG = 1
[Setting condition]
When a rising edge is detected on the CSYNCI pin
4HFEDG0 R/(W)
*
1
HFBACKI Edge
Detects a rising edge on the HFBACKI pin.
[Clearing condition]
When 0 is written in HFEDG after reading HFEDG = 1
[Setting condition]
When a rising edge is detected on the HFBACKI pin