Datasheet

Section 13 Timer Connection
Rev. 3.00 Mar 21, 2006 page 323 of 788
REJ09B0300-0300
13.3.2 Timer Connection Register O (TCONRO)
TCONRO controls output signal output, phase inversion, etc.
Bit Bit Name Initial Value R/W Description
7
6
5
4
HOE
VOE
CLOE
CBOE
0
0
0
0
R/W
R/W
R/W
R/W
Output Enable
These bits control enabling/disabling of output of
horizontal synchronization signal (HSYNCO), vertical
synchronization signal (VSYNCO), clamp waveform
(CLAMPO), and blanking waveform (CBLANK). When
output is disabled, the state of the relevant pin is
determined by port DR and DDR, FRT, TMR, and
PWM settings.
Output enabling/disabling control does not affect the
port, FRT, or TMR input functions, but some FRT and
TMR input signal sources are determined by the
SCONE bit in TCONRI.
HOE:
0: The P44/TMO1/HIRQ1/HSYNCO pin functions as
the P44/TMO1/HIRQ1 pin
1: The P44/TMO1/HIRQ1/HSYNCO pin functions as
the HSYNCO pin
VOE:
0: The P61/FTOA/CIN1/KIN1/VSYNCO pin functions
as the P61/FTOA/CIN1/KIN1 pin
1: The P61/FTOA/CIN1/KIN1/VSYNCO pin functions
as the VSYNCO pin
CLOE:
0: The P64/FTIC/CIN4/KIN4/CLAMPO pin functions
as the P64/FTIC/CIN4/KIN4 pin
1: The P64/FTIC/CIN4/KIN4/CLAMPO pin functions
as the CLAMPO pin
CBOE:
0: The P27/A15/PW15/CBLANK pin functions as the
P27/A15/PW15 pin
In mode 1:
1: The P27/A15/PW15/CBLANK pin functions as the
A15 pin
In modes 2 and 3:
1: The P27/A15/PW15/CBLANK pin functions as the
CBLANK pin