Datasheet

Section 12 8-Bit Timer (TMR)
Rev. 3.00 Mar 21, 2006 page 307 of 788
REJ09B0300-0300
Input Capture Signal Input Timing: Figure 12.11 shows the timing of the input capture
operation.
φ
TMRIX
Input capture
signal
TCNTX
n
nn
m
M
m
N + 1N
N
n + 1
TICRR
TICRF
Figure 12.11 Timing of Input Capture Operation
If the input capture signal is input while TICRR and TICRF are being read, the input capture
signal is delayed by one system clock (φ) cycle. Figure 12.12 shows the timing of this operation.
φ
TMRIX
TICRR, TICRF read cycle
T
1
T
2
Input capture
signal
Figure 12.12 Timing of Input Capture Signal
(Input Capture Signal Is Input during TICRR and TICRF Read)