Datasheet

Section 12 8-Bit Timer (TMR)
Rev. 3.00 Mar 21, 2006 page 302 of 788
REJ09B0300-0300
12.5 Operation Timing
12.5.1 TCNT Count Timing
Figure 12.4 shows the TCNT count timing with an internal clock source. Figure 12.5 shows the
TCNT count timing with an external clock source. The pulse width of the external clock signal
must be at least 1.5 system clocks (φ) for a single edge and at least 2.5 system clocks (φ) for both
edges. The counter will not increment correctly if the pulse width is less than these values.
φ
Internal clock
TCNT input
clock
TCNT
N – 1 N N + 1
Figure 12.4 Count Timing for Internal Clock Input
φ
External clock
input pin
TCNT input
clock
TCNT
N – 1 N N + 1
Figure 12.5 Count Timing for External Clock Input (Both Edges)