Datasheet

Section 11 16-Bit Free-Running Timer (FRT)
Rev. 3.00 Mar 21, 2006 page 283 of 788
REJ09B0300-0300
φ
Address
OCRAR (OCRAF)
address
Internal write signal
Compare-match signal
FRC
Automatic addition is not performed
because compare-match signals are disabled.
Disabled
OCRA N
N N+1
OCRAR (OCRAF)
Old data New data
T
1
T
2
Write cycle of OCRAR/OCRAF
Figure 11.20 Conflict between OCRAR/OCRAF Write and Compare-Match
(When Automatic Addition Function Is Used)