Datasheet

Section 10 14-Bit PWM Timer (PWMX)
Rev. 3.00 Mar 21, 2006 page 254 of 788
REJ09B0300-0300
t
f1
t
f2
t
f255
t
f256
t
H1
t
H2
t
H3
t
H255
t
H256
1 conversion cycle
t
f1
= t
f2
= t
f3
= ··· = t
f255
= t
f256
= T× 64
t
H1
+ t
H2
+ t
H3
+ ··· + t
H255
+ t
H256
= T
H
t
f1
t
f2
t
f63
t
f64
t
H1
t
H2
t
H3
t
H63
t
H64
1 conversion cycle
t
f1
= t
f2
= t
f3
= ··· = t
f63
= t
f64
= T× 256
t
H1
+ t
H2
+ t
H3
+ ··· + t
H63
+ t
H64
= T
H
a. CFS = 0 [base cycle = resolution (T) × 64]
b. CFS = 1 [base cycle = resolution (T) × 256]
Figure 10.4 Output Waveform (OS = 1, DADR Corresponds to T
H
)
An example of setting CFS to 1 (basic cycle = resolution (T) × 256) and OS to 1 (PWMX inverted
output) is shown as an additional pulse. When CFS is set to 1, the duty ratio of the basic pulse is
determined by the upper eight bits (DA13 to DA6) in DADR, and the position of the additional
pulse is determined by the following six bits (DA5 to DA0) as shown in figure 10.5.
Table 10.4 shows the position of the additional pulse.
Basic pulse duty ratio
DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS
11
Additional pulse position
Figure 10.5 D/A Data Register Configuration when CFS = 1
Here, the case of DADR = H'0207 (B’0000 0010 0000 0111) is considered. Figure 10.6 shows an
output waveform. Because CFS = 1 and the value of upper eight bits is B’0000 0010, the duty
ratio of the basic pulse is 2/256 × (T) of high width.