Datasheet

Section 10 14-Bit PWM Timer (PWMX)
Rev. 3.00 Mar 21, 2006 page 252 of 788
REJ09B0300-0300
Table 10.3 summarizes the relationships between the CKS, CFS, and OS bit settings and the
resolution, base cycle, and conversion cycle. The PWM output remains fixed unless DADR
contains at least a certain minimum value.
Table 10.3 Settings and Operation (Examples when φ
φφ
φ = 10 MHz)
Fixed DADR Bits
Bit DataCKS
Resolution
T
(µs)
CFS
Base
Cycle
(µs)
Conversion
Cycle
(µs)
T
L
(if OS = 0)
T
H
(if OS = 1)
Precision
(Bits)
3210
Conversion
Cycle
*
(µs)
14 1638.4
12 0 0 409.6
06.4
1. Always low (or high)
(DADR = H'0001 to
H'03FD)
2. (Data value) × T
(DADR = H'0401 to
H'FFFD)
10 0000 102.4
14 1638.4
12 0 0 409.6
00.1
1 25.6
1638.4
1. Always low (or high)
(DADR = H'0003 to
H'00FF)
2. (Data value) × T
(DADR = H'0103 to
H'FFFF)
10 0000 102.4
14 3276.8
12 0 0 819.2
0 12.8
1. Always low (or high)
(DADR = H'0001 to
H'03FD)
2. (Data value) × T
(DADR = H'0401 to
H'FFFD)
10 0000 204.8
14 3276.8
12 0 0 819.2
10.2
1 51.2
3276.8
1. Always low (or high)
(DADR = H'0003 to
H'00FF)
2. (Data value) × T
(DADR = H'0103 to
H'FFFF)
10 0000 204.8
Note: * This column indicates the conversion cycle when specific DADR bits are fixed.