Datasheet

Section 10 14-Bit PWM Timer (PWMX)
Rev. 3.00 Mar 21, 2006 page 245 of 788
REJ09B0300-0300
10.3.1 PWM (D/A) Counters H and L (DACNTH, DACNTL)
DACNT is a 14-bit readable/writable up-counter. The input clock is selected by the clock select bit
(CKS) in DACR. DACNT functions as the time base for both PWM (D/A) channels. When a
channel operates with 14-bit precision, it uses all DACNT bits. When a channel operates with 12-
bit precision, it uses the lower 12 bits and ignores the upper two bits. Since DACNT consists of
16-bit data, DACNT transfers data to the CPU via the temporary register (TEMP). For details,
refer to section 10.4, Bus Master Interface.
15
7
DACNTH DACNTL
14
6
13
5
12
4
11
3
10
2
9
1
8
0
7
8
6
9
5
10
4
11
3
12
2
13
1
—
0
—
Bit (CPU)
Bit (Counter)
:
:
—
REGS
• DACNTH
Bit Bit Name Initial Value R/W Description
7
to
0
UC7
to
UC0
All 0 R/W Upper Up-Counter
• DACNTL
Bit Bit Name Initial Value R/W Description
7
to
2
UC8
to
UC13
All 0 R/W Lower Up-Counter
1 — 1RReserved
This bit is always read as 1 and cannot be modified.
0 REGS 1 R/W Register Select
DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. The REGS bit specifies
which registers can be accessed.
0: DADRA and DADRB can be accessed
1: DACR and DACNT can be accessed