Datasheet

Rev. 3.00 Mar 21, 2006 page xxiv of liv
6.5.3 Basic Operation Timing....................................................................................... 131
6.5.4 Wait Control ........................................................................................................ 139
6.6 Burst ROM Interface......................................................................................................... 141
6.6.1 Basic Operation Timing....................................................................................... 141
6.6.2 Wait Control ........................................................................................................ 142
6.7 Idle Cycle.......................................................................................................................... 142
6.8 Bus Arbitration.................................................................................................................. 144
6.8.1 Priority of Bus Masters........................................................................................ 144
6.8.2 Bus Transfer Timing............................................................................................ 144
Section 7 Data Transfer Controller (DTC)................................................................... 145
7.1 Features............................................................................................................................. 145
7.2 Register Descriptions........................................................................................................ 147
7.2.1 DTC Mode Register A (MRA) ............................................................................ 147
7.2.2 DTC Mode Register B (MRB)............................................................................. 149
7.2.3 DTC Source Address Register (SAR).................................................................. 149
7.2.4 DTC Destination Address Register (DAR).......................................................... 149
7.2.5 DTC Transfer Count Register A (CRA) .............................................................. 150
7.2.6 DTC Transfer Count Register B (CRB)............................................................... 150
7.2.7 DTC Enable Registers (DTCER)......................................................................... 150
7.2.8 DTC Vector Register (DTVECR)........................................................................ 151
7.3 Activation Sources............................................................................................................ 152
7.4 Location of Register Information and DTC Vector Table ................................................ 153
7.5 Operation .......................................................................................................................... 155
7.5.1 Normal Mode....................................................................................................... 156
7.5.2 Repeat Mode........................................................................................................ 157
7.5.3 Block Transfer Mode........................................................................................... 158
7.5.4 Chain Transfer ..................................................................................................... 159
7.5.5 Interrupts.............................................................................................................. 160
7.5.6 Operation Timing................................................................................................. 160
7.5.7 Number of DTC Execution States........................................................................ 161
7.6 Procedures for Using DTC................................................................................................ 163
7.6.1 Activation by Interrupt......................................................................................... 163
7.6.2 Activation by Software ........................................................................................ 163
7.7 Examples of Use of DTC.................................................................................................. 164
7.7.1 Normal Mode....................................................................................................... 164
7.7.2 Software Activation ............................................................................................. 165
7.8 Usage Notes ...................................................................................................................... 166
7.8.1 Module Stop Mode Setting .................................................................................. 166
7.8.2 On-Chip RAM ..................................................................................................... 166
7.8.3 DTCE Bit Setting................................................................................................. 166