Datasheet

Section 8 I/O Ports
Rev. 3.00 Mar 21, 2006 page 196 of 788
REJ09B0300-0300
8.9.2 Port 8 Data Register (P8DR)
P8DR stores output data for the port 8 pins (P86 to P80).
Bit Bit Name Initial Value R/W Description
7— 1 — Reserved
The initial value must not be changed.
6 P86DR 0 R/W
5 P85DR 0 R/W
4 P84DR 0 R/W
3 P83DR 0 R/W
2 P82DR 0 R/W
1 P81DR 0 R/W
0 P80DR 0 R/W
If a port 8 read is performed while P8DDR bits are
set to 1, the P8DR values are read directly,
regardless of the actual pin states. If a port 8 read
is performed while P8DDR bits are cleared to 0,
the pin states are read.
8.9.3 Pin Functions
• P86/IRQ5/ SCK1/SCL1
The pin function is switched as shown below according to the combination of the CKE1 and
CKE0 bits in SCR of SCI_1, the C/A bit in SMR of SCI_1, the ICE bit in ICCR of IIC_1, and
the P86DDR bit.
ICE 0 1
CKE1 0 1 0
C/A 01—0
CKE0 0 1 — — 0
P86DDR 0 1 ————
P86
input pin
P86
output pin
SCK1
output pin
SCK1
output pin
SCK1
input pin
SCL1
I/O pin
Pin Function
IRQ5 input pin
*
Note: * When the IRQ5E bit in IER is set to 1, this pin is used as the IRQ5 input pin. When this
pin is used as the SCL1 I/O pin, bits CKE1 and CKE0 in SCR of SCI_1 and bit C/A in
SMR of SCI_1 must all be cleared to 0. When the P86 output pin and SCK1 output pin
are set, the output type is NMOS push-pull output. SCL1 is an NMOS-only output, and
has direct bus drive capability.