Datasheet

Section 8 I/O Ports
Rev. 3.00 Mar 21, 2006 page 187 of 788
REJ09B0300-0300
8.6.2 Port 5 Data Register (P5DR)
P5DR stores output data for port 5 pins.
Bit Bit Name Initial Value R/W Description
7
to
3
— All 1 — Reserved
The initial value must not be changed.
2 P52DR 0 R/W
1 P51DR 0 R/W
0 P50DR 0 R/W
If a port 5 read is performed while P5DDR bits are
set to 1, the P5DR values are read directly,
regardless of the actual pin states. If a port 5 read
is performed while P5DDR bits are cleared to 0,
the pin states are read.
8.6.3 Pin Functions
• P52/SCK0/SCL0
The pin function is switched as shown below according to the combination of the CKE1 and
CKE0 bits in SCR of SCI_0, the C/A bit in SMR of SCI_0, the ICE bit in ICCR of IIC_0, and
the P52DDR bit.
ICE 0 1
CKE1 0 1 0
C/A 01—0
CKE0 0 1 — — 0
P52DDR0 1 ————
Pin Function P52
input pin
P52
output pin
SCK0
output pin
SCK0
output pin
SCK0
input pin
SCL0
I/O pin
Note: When this pin is used as the SCL0 I/O pin, bits CKE1 and CKE0 in SCR of SCI0 and bit C/A
in SMR of SCI0 must all be cleared to 0.
SCL0 is an NMOS open-drain output, and has direct bus drive capability.
When set as the P52 output pin or SCK0 output pin, this pin is an NMOS push-pull output.