Datasheet

Rev. 3.00 Mar 21, 2006 page xxii of liv
2.7.8 Memory Indirect—@@aa:8 ................................................................................ 54
2.7.9 Effective Address Calculation ............................................................................. 55
2.8 Processing States............................................................................................................... 57
2.9 Usage Notes ...................................................................................................................... 59
2.9.1 Note on TAS Instruction Usage........................................................................... 59
2.9.2 Note on STM/LDM Instruction Usage ................................................................ 59
2.9.3 Note on Bit Manipulation Instructions................................................................. 59
2.9.4 EEPMOV Instruction........................................................................................... 61
Section 3 MCU Operating Modes .................................................................................. 63
3.1 MCU Operating Mode Selection ...................................................................................... 63
3.2 Register Descriptions........................................................................................................63
3.2.1 Mode Control Register (MDCR) ......................................................................... 64
3.2.2 System Control Register (SYSCR)...................................................................... 65
3.2.3 Serial Timer Control Register (STCR) ................................................................ 66
3.3 Operating Mode Descriptions ........................................................................................... 69
3.3.1 Mode 1................................................................................................................. 69
3.3.2 Mode 2................................................................................................................. 69
3.3.3 Mode 3................................................................................................................. 69
3.3.4 Pin Functions in Each Operating Mode ............................................................... 70
3.4 Address Map in Each Operating Mode............................................................................. 71
Section 4 Exception Handling ......................................................................................... 81
4.1 Exception Handling Types and Priority............................................................................ 81
4.2 Exception Sources and Exception Vector Table............................................................... 82
4.3 Reset.................................................................................................................................. 83
4.3.1 Reset Exception Handling.................................................................................... 83
4.3.2 Interrupts after Reset............................................................................................ 84
4.3.3 On-Chip Peripheral Modules after Reset Is Cancelled ........................................ 84
4.4 Interrupt Exception Handling............................................................................................ 85
4.5 Trap Instruction Exception Handling................................................................................ 85
4.6 Stack Status after Exception Handling.............................................................................. 86
4.7 Usage Note........................................................................................................................ 87
Section 5 Interrupt Controller .......................................................................................... 89
5.1 Features............................................................................................................................. 89
5.2 Input/Output Pins.............................................................................................................. 91
5.3 Register Descriptions........................................................................................................91
5.3.1 Interrupt Control Registers A to C (ICRA to ICRC)............................................ 92
5.3.2 Address Break Control Register (ABRKCR)....................................................... 93
5.3.3 Break Address Registers A to C (BARA to BARC)............................................ 94