Datasheet

Section 7 Data Transfer Controller (DTC)
Rev. 3.00 Mar 21, 2006 page 162 of 788
REJ09B0300-0300
Table 7.5 DTC Execution Status
Mode
Vector Read
I
Register Information
Read/Write
J
Data Read
K
Data Write
L
Internal
Operations
M
Normal1 6 113
Repeat 1 6 1 1 3
Block transfer 1 6 N N 3
N: Block size (initial setting of CRAH and CRAL)
Table 7.6 Number of States Required for Each Execution Status
Object to be Accessed
On-
Chip
RAM
On-
Chip
ROM
On-Chip I/O
Registers
External Devices
Bus width 3216816 8 16
Access states 11222323
Vector read S
I
— 1 —— 4 6 + 2m 2 3 + m
Register information
read/write S
J
1 ———————
Byte data read S
K
112223 + m23 + m
Word data read S
K
114246 + 2m23 + m
Byte data write S
L
112223 + m23 + m
Word data write S
L
114246 + 2m23 + m
Execution
status
Internal operation S
M
1
The number of execution states is calculated from using the formula below. Note that Σ is the sum
of all transfers activated by one activation source (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · S
I
+ Σ (J · S
J
+ K · S
K
+ L · S
L
) + M · S
M
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from on-chip ROM to an internal I/O register, then the time required for the
DTC operation is 13 states. The time from activation to the end of data write is 10 states.