Datasheet

Section 7 Data Transfer Controller (DTC)
Rev. 3.00 Mar 21, 2006 page 146 of 788
REJ09B0300-0300
Internal address bus
DTCER
A
to
DTCER
E
DTVECR
Interrupt controller DTC On-chip RAM
Internal data bus
CPU interrupt
request
MRA MRB
CRA CRB
DAR
SAR
Interrupt
request
MRA, MRB
CRA, CRB
SAR
DAR
DTCERA to DTCERE
DTVECR
: DTC mode register A, B
: DTC transfer count register A, B
: DTC source address register
: DTC destination register
: DTC enable registers A to E
: DTC vector register
Legend:
DTC activation request
Control logic
Register information
Figure 7.1 Block Diagram of DTC