Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 21, 2006 page 142 of 788
REJ09B0300-0300
T
1
Address bus
φ
Data bus
T
2
T
1
T
1
Full access
RD
Burst access
Only lower
address changes
Read data Read data Read data
AS
/
IOS
(IOSE = 0)
Figure 6.15 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0)
6.6.2 Wait Control
As with the basic bus interface, program wait insertion or pin wait insertion using the WAIT pin
can be used in the initial cycle (full access) of the burst ROM interface. For details, see section
6.5.4, Wait Control. Wait states cannot be inserted in a burst cycle.
6.7 Idle Cycle
When this LSI accesses the external address space, it can insert a 1-state idle cycle (T
I
) between
bus cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is
possible, for example, to avoid data collisions between ROM with a long output floating time, and
high-speed memory and I/O interfaces.
If an external write occurs after an external read while the ICIS0 bit is set to 1 in BCR, an idle
cycle is inserted at the start of the write cycle.
Figure 6.16 shows examples of idle cycle operation. In these examples, bus cycle A is a read cycle
for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In figure 6.16 (a),
with no idle cycle inserted, a collision occurs in bus cycle B between the read data from ROM and
the CPU write data. In figure 6.16 (b), an idle cycle is inserted, thus preventing data collision.