Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 21, 2006 page 140 of 788
REJ09B0300-0300
By program wait
T
1
Address bus
φ
AS/IOS (IOSE = 0)
RD
Data bus
Read data
Read
HWR, LWR
Write data
Write
Note: ↓ shown in φ clock indicates the WAIT pin sampling timing.
WAIT
Data bus
T
2
T
W
T
W
T
W
T
3
By WAIT pin
Figure 6.13 Example of Wait State Insertion Timing (Pin Wait Mode)