Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 21, 2006 page 131 of 788
REJ09B0300-0300
6.5.3 Basic Operation Timing
8-Bit, 2-State Access Space: Figure 6.5 shows the bus timing for an 8-bit, 2-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait
states cannot be inserted.
Bus cycle
T
1
T
2
Address bus
φ
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
D15 to D8
Valid
D7 to D0
Invalid
Read
HWR
D15 to D8
Valid
Write
Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space