Datasheet

Section 5 Interrupt Controller
Rev. 3.00 Mar 21, 2006 page 92 of 788
REJ09B0300-0300
5.3.1 Interrupt Control Registers A to C (ICRA to ICRC)
The ICR registers set interrupt control levels for interrupts other than NMI and address breaks.
The correspondence between interrupt sources and ICRA to ICRC settings is shown in table 5.2.
Bit Bit Name Initial Value R/W Description
7
to
0
ICRn7
to
IRCn0
All 0 R/W Interrupt Control Level
0: Corresponding interrupt source is interrupt
control level 0 (no priority)
1: Corresponding interrupt source is interrupt
control level 1 (priority)
n: A to C
Table 5.2 Correspondence between Interrupt Source and ICR
Register
Bit Bit Name ICRA ICRB ICRC
7 ICRn7 IRQ0 A/D converter SCI_0
6 ICRn6 IRQ1 FRT SCI_1
5 ICRn5 IRQ2, IRQ3 — SCI_2
4 ICRn4 IRQ4, IRQ5 — IIC_0
3 ICRn3 IRQ6, IRQ7 TMR_0 IIC_1
2 ICRn2 DTC TMR_1 —
1 ICRn1 WDT_0 TMR_X, TMR_Y LPC
*
0 ICRn0 WDT_1 XBS,
Keyboard buffer controller
—
Legend:
: Reserved. The write value should always be 0.
Notes: n: A to C
* On products not including LPC, this bit is reserved. The write value should always be 0.