Datasheet

Section 3 MCU Operating Modes
Rev. 3.00 Mar 21, 2006 page 68 of 788
REJ09B0300-0300
Bit Bit Name Initial Value R/W Description
3 FLSHE 0 R/W Flash Memory Control Register Enable
Enables or disables CPU access for flash memory
registers (FLMCR1, FLMCR2, EBR1, EBR2), control
registers in power-down state (SBYCR, LPWRCR,
MSTPCRH, MSTPCRL), and control registers of on-
chip peripheral modules (PCSR, SYSCR2).
0: Registers in power-down state and control
registers of on-chip peripheral modules are
accessed in an area from H'(FF)FF80 to
H'(FF)FF87.
1: Control registers of flash memory are accessed in
an area from H'(FF)FF80 to H'(FF)FF87.
2— 0 R/(W)Reserved
The initial value should not be changed.
1
0
ICKS1
ICKS0
0
0
R/W
R/W
Internal Clock Source Select 1, 0
These bits select a clock to be input to the timer
counter (TCNT) and a count condition together with
bits CKS2 to CKS0 in the timer control register
(TCR). For details, refer to section 12.3.4, Timer
Control Register (TCR).