Datasheet

Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 856 of 1130
REJ09B0327-0400
Table 26.37 Timing of On-Chip Supporting Modules (2)
Condition A: V
CC
= 5.0 V ±10%, V
CC
B = 5.0 V ±10%, V
SS
= 0 V, φ = 2 MHz to maximum
operating frequency, T
a
= –20 to +75°C
Condition B: V
CC
= 3.0 V to 5.5 V, V
CC
B = 3.0 V to 5.5 V, V
SS
= 0 V, φ = 2 MHz to maximum
operating frequency, T
a
= –20 to +75°C
Condition A Condition B
20 MHz 10 MHz
Item Symbol Min Max Min
Max
Unit
Test
Conditions
HIF read
cycle
CS/HA0 setup
time
t
HAR
10 — 10 — ns Figure
26.26
CS/HA0 hold time t
HRA
10 — 10 — ns
IOR pulse width t
HRPW
120 — 220 — ns
HDB delay time t
HRD
— 100 — 200 ns
HDB hold time t
HRF
0 25 0 40 ns
HIRQ delay time t
HIRQ
— 120 — 200 ns
HIF write
cycle
CS/HA0 setup
time
t
HAW
10 — 10 — ns
CS/HA0 hold time t
HWA
10 — 10 — ns
IOW pulse width t
HWPW
60 — 100 — ns
HDB
setup
time
Fast A20
gate not
used
t
HDW
30 — 50 — ns
Fast A20
gate used
45 — 85 — ns
HDB hold time t
HWD
15 — 25 — ns
GA20 delay time t
HGA
— 90 — 180 ns