Datasheet

Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 567 of 1130
REJ09B0327-0400
17.2.3 Keyboard Data Buffer Register (KBBR)
Bit 76543210
KB7 KB6 KB5 KB4 KB3 KB2 KB1 KB0
Initial value00000000
Read/Write RRRRRRRR
KBBR is a read-only register that stores receive data. Its value is valid only when KBF = 1.
KBBR is initialized to H'00 by a reset, in standby mode, watch mode, subactive mode, subsleep
mode, and module stop mode, and when KBIOE is cleared to 0.
17.2.4 Module Stop Control Register (MSTPCR)
7
MSTP15
0
R/W
Bit
Initial value
Read/Write
6
MSTP14
0
R/W
5
MSTP13
1
R/W
4
MSTP12
1
R/W
3
MSTP11
1
R/W
2
MSTP10
1
R/W
1
MSTP9
1
R/W
0
MSTP8
1
R/W
7
MSTP7
1
R/W
6
MSTP6
1
R/W
5
MSTP5
1
R/W
4
MSTP4
1
R/W
3
MSTP3
1
R/W
2
MSTP2
1
R/W
1
MSTP1
1
R/W
0
MSTP0
1
R/W
MSTPCRH MSTPCRL
MSTPCR, comprising two 8-bit readable/writable register, performs module stop mode control.
When the MSTP2 bit is set to 1, the keyboard buffer controller halts and enters module stop mode.
See section 25.5, Module Stop Mode, for details.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRL Bit 2—Module Stop (MSTP2): Specifies keyboard buffer controller module stop
mode.
MSTPCRL
Bit 2
MSTP2 Description
0 Keyboard buffer controller module stop mode is cleared
1 Keyboard buffer controller module stop mode is set (Initial value)