Datasheet

Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 203 of 1130
REJ09B0327-0400
Table 7.9 Number of States Required for Each Execution Phase
Object of Access
On-
Chip
RAM
On-
Chip
ROM
Internal I/O
Registers External Devices
Bus width 32 16 8 16 8 8 16 16
Access states 1 1 2 2 2 3 2 3
Vector read S
I
— 1 ——46+2m23+mExecution
phase
Register
information
read/write
S
J
1 ————— ——
Byte data read S
K
112223+m23+m
Word data read S
K
114246+2m23+m
Byte data write S
L
112223+m23+m
Word data write S
L
114246+2m23+m
Internal operation S
M
111111 11
The number of execution states is calculated from the formula below. Note that Σ means the sum
of all transfers activated by one activation event (the number for which the CHNE bit is set to one,
plus 1).
Number of execution states = I · S
I
+ Σ (J · S
J
+ K · S
K
+ L · S
L
) + M · S
M
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from the on-chip ROM to an internal I/O register, the time required for the
DTC operation is 13 states. The time from activation to the end of the data write is 10 states.