Datasheet

Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 181 of 1130
REJ09B0327-0400
7.1.3 Register Configuration
Table 7.1 summarizes the DTC registers.
Table 7.1 DTC Registers
Name Abbreviation R/W Initial Value Address
*
1
DTC mode register A MRA —
*
2
Undefined —
*
3
DTC mode register B MRB —
*
2
Undefined —
*
3
DTC source address register SAR —
*
2
Undefined —
*
3
DTC destination address register DAR —
*
2
Undefined —
*
3
DTC transfer count register A CRA —
*
2
Undefined —
*
3
DTC transfer count register B CRB —
*
2
Undefined —
*
3
DTC enable registers DTCER
*
4
R/W H'00 H'FEEE to H'FEF2
DTC vector register DTVECR
*
4
R/W H'00 H'FEF3
Module stop control register MSTPCRH R/W H'3F H'FF86
MSTPCRL R/W H'FF H'FF87
Notes: 1. Lower 16 bits of the address.
2. Registers within the DTC cannot be read or written to directly.
3. Allocated to on-chip RAM addresses H'EC00 to H'EFFF as register information.
They cannot be located in external memory space.
When the DTC is used, do not clear the RAME bit in SYSCR to 0.
4. The H8S/2144 Group and H8S/2147N do not include an on-chip DTC, and therefore the
DTCER and DTVECR register addresses should not be accessed by the CPU.