Datasheet

Section 5 Interrupt Controller
Rev. 4.00 Sep 27, 2006 page 124 of 1130
REJ09B0327-0400
If any of bits KMIMR15 to KMIMR8 is cleared to 0, interrupt input from the IRQ7 pin will be
ignored. When pins KIN7 to KIN0 or KIN15 to KIN8 are used as key-sense interrupt input pins,
either low-level sensing or falling-edge sensing must be designated as the interrupt sense condition
for the corresponding interrupt source (IRQ6 or IRQ7).
5.2.8 Address Break Control Register (ABRKCR)
7
CMF
0
R
6
—
0
—
5
—
0
—
4
—
0
—
3
—
0
—
0
BIE
0
R/W
2
—
0
—
1
—
0
—
Bit
Initial value
Read/Write
ABRKCR is an 8-bit readable/writable register that performs address break control.
ABRKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Condition Match Flag (CMF): This is the address break source flag, used to indicate that
the address set by BAR has been prefetched. When the CMF flag and BIE flag are both set to 1, an
address break is requested.
Bit 7
CMF Description
0 [Clearing condition]
When address break interrupt exception handling is executed (Initial value)
1 [Setting condition]
When address set by BARA to BARC is prefetched while BIE = 1
Bits 6 to 1—Reserved: These bits cannot be modified and are always read as 0.
Bit 0—Break Interrupt Enable (BIE): Selects address break enabling or disabling.
Bit 0
BIE Description
0 Address break disabled (Initial value)
1 Address break enabled