Datasheet

Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1049 of 1130
REJ09B0327-0400
TCSR0—Timer Control/Status Register 0 H'FFA8 WDT0
7
OVF
0
R/(W)
*
6
WT/IT
0
R/W
5
TME
0
R/W
4
RSTS
0
R/W
3
RST/NMI
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Bit
Initial value
Read/Write
Clock select 2 to 0
CKS2
0
1
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
CKS1
0
1
0
1
CKS0
0
1
0
1
0
1
0
1
Note: * Only 0 can be written, to clear the flag.
Note: * When OVF is polled and the interval timer interrupt is disabled,
OVF = 1 must be read at least twice.
Clock
Reset or NMI
0 NMI interrupt requested
1 Internal reset requested
Timer enable
0 TCNT is initialized to H'00 and halted
1 TCNT counts
Reserved bit
Timer mode select
0
Interval timer mode: Sends the CPU an interval timer interrupt
request (WOVI) when TCNT overflows
1 Watchdog timer mode: Generates a reset or NMI interrupt when
TCNT overflows
Overflow flag
0 [Clearing conditions]
• Write 0 in the TME bit
• Read TCSR when OVF = 1
*
, then write 0 in OVF
1 [Setting condition]
When TCNT overflows (changes from H'FF to H'00)
(When internal reset request generation is selected in watchdog
timer mode, OVF is cleared automatically by the internal reset.)