Datasheet

Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1038 of 1130
REJ09B0327-0400
SARX1—Second Slave Address Register 1 H'FF8E IIC1
SAR1—Slave Address Register 1 H'FF8F IIC1
SARX0—Second Slave Address Register 0 H'FFDE IIC0
SAR0—Slave Address Register 0 H'FFDF IIC0
7
SVA6
0
R/W
6
SVA5
0
R/W
5
SVA4
0
R/W
4
SVA3
0
R/W
3
SVA2
0
R/W
0
FS
0
R/W
2
SVA1
0
R/W
1
SVA0
0
R/W
Bit
Initial value
Read/Write
SAR
SARX
Slave address
Format select
Second slave address
7
SVAX6
0
R/W
6
SVAX5
0
R/W
5
SVAX4
0
R/W
4
SVAX3
0
R/W
3
SVAX2
0
R/W
0
FSX
1
R/W
2
SVAX1
0
R/W
1
SVAX0
0
R/W
Bit
Initial value
Read/Write
Note: *
Format select
DDCSWR
Bit 6
SW
SAR
Bit 0
FS
SARX
Bit 0
FSX
Operating Mode
I
2
C bus format
• SAR and SARX slave addresses recognized
0 00
I
2
C bus format
• SAR slave address recognized
• SARX slave address ignored
I
2
C bus format
• SAR slave address ignored
• SARX slave address recognized
Synchronous serial format
• SAR and SARX slave addresses ignored
Formatless mode (start/stop conditions not
detected)
• Acknowledge bit used
Formatless mode
*
(start/stop conditions not detected)
• No acknowledge bit
1
10
1
100
1
10
1
Do not set this mode when automatic switching to the I
2
C bus format is
performed by means of the DDCSWR setting.