Datasheet

Appendix B Internal I/O Registers
Rev. 4.00 Sep 27, 2006 page 1009 of 1130
REJ09B0327-0400
STR3—Status Register 3 H'FE86 HIF
STR4—Status Register 4 H'FE8E HIF
7
DBU
0
R/W
R
6
DBU
0
R/W
R
5
DBU
0
R/W
R
4
DBU
0
R/W
R
3
C/D
0
R
R
0
OBF
0
R/(W)
R
2
DBU
0
R/W
R
1
IBF
0
R
R
Bit
Initial value
Slave R/W
Host R/W
Output buffer full
0 [Clearing condition]
When the host processor
reads ODR or the slave
writes 0 in the OBF bit
1 [Setting condition]
When the slave processor
writes to ODR
User-defined bits
Input buffer full
0 [Clearing condition]
When the slave processor reads IDR
1 [Setting condition]
When the host processor writes to IDR
Command/data
0 Contents of input data register (IDR) are data
1 Contents of input data register (IDR) are a command