Datasheet

Section 18 Host Interface X-Bus Interface (XBS)
Rev. 3.00 Mar 21, 2006 page 518 of 788
REJ09B0300-0300
18.3.5 Status Register (STR)
STR indicates status information during host interface processing.
R/W
Bit Bit Name
Initial
Value Slave Host Description
7 to 4 DBU All 0 R/W R Defined by User
The user can use these bits as necessary.
3C/D 0 R R Command/Data
Receives the HA0 input when the host processor
writes to IDR, and indicates whether IDR
contains data or a command.
0: Contents of input data register (IDR) are data
1: Contents of input data register (IDR) are a
command
2 DBU 0 R/W R Defined by User
The user can use these bits as necessary.
1 IBF 0 R R Input Buffer Full
This bit is an internal interrupt source to the slave
processor (this LSI).
The IBF flag setting and clearing conditions are
different when the fast A20 gate is used. For
details see table 18.5.
[Clearing Condition]
0: When the slave processor reads IDR
[Setting Condition]
1: When the host processor writes to IDR
0OBF 0 R/(W)
*
R Output Buffer Full
[Clearing Condition]
0: When the host processor reads ODR or the
slave writes 0 in the OBF bit
[Setting Condition]
1: When the slave processor writes to ODR
Note: * Only 0 can be written, to clear the flag.