Datasheet

Section 16 I
2
C Bus Interface (IIC) (Optional)
Rev. 3.00 Mar 21, 2006 page 472 of 788
REJ09B0300-0300
Table 16.7 Examples of Operation Using DTC
Item
Master Transmit
Mode
Master Receive
Mode
Slave Transmit
Mode
Slave Receive
Mode
Slave address +
R/W bit
transmission/
reception
Transmission by
DTC (ICDR write)
Transmission by
CPU (ICDR write)
Reception by
CPU (ICDR read)
Reception by CPU
(ICDR read)
Dummy data
read
— Processing by
CPU (ICDR read)
——
Actual data
transmission/
reception
Transmission by
DTC (ICDR write)
Reception by
DTC (ICDR read)
Transmission by
DTC (ICDR write)
Reception by DTC
(ICDR read)
Dummy data
(H'FF) write
——Processing by
DTC (ICDR write)
—
Last frame
processing
Not necessary Reception by
CPU (ICDR read)
Not necessary Reception by CPU
(ICDR read)
Transfer request
processing after
last frame
processing
1st time: Clearing
by CPU
2nd time: Stop
condition issuance
by CPU
Not necessary Automatic clearing
on detection of stop
condition during
transmission of
dummy data (H'FF)
Not necessary
Setting of
number of DTC
transfer data
frames
Transmission:
Actual data count
+ 1 (+1 equivalent
to slave address +
R/W bits)
Reception: Actual
data count
Transmission:
Actual data count
+ 1 (+1 equivalent
to dummy data
(H'FF))
Reception: Actual
data count
16.4.10 Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 16.29 shows a block diagram of the noise canceler.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) pin
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.