Datasheet

Section 12 8-Bit Timer (TMR)
Rev. 3.00 Mar 21, 2006 page 305 of 788
REJ09B0300-0300
12.5.6 Timing of Overflow Flag (OVF) Setting
The OVF bit in TCSR is set to 1 when the TCNT overflows (changes from H'FF to H'00). Figure
12.10 shows the timing of OVF flag setting.
φ
OVF
Overflow signal
TCNT H'FF H'00
Figure 12.10 Timing of OVF Flag Setting
12.6 Operation with Cascaded Connection
If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, a single 16-bit timer can be used (16-bit count
mode) or the compare-matches of the 8-bit timer of channel 0 can be counted by the 8-bit timer of
channel 1 (compare-match count mode).
12.6.1 16-Bit Count Mode
When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer
with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
Setting of Compare-Match Flags:
• The CMF flag in TCSR_0 is set to 1 when a 16-bit compare-match occurs.
• The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare-match occurs.