Datasheet

Rev. 3.00 Mar 21, 2006 page xxxi of liv
15.6.2 SCI Initialization (Clocked Synchronous Mode)................................................. 394
15.6.3 Serial Data Transmission (Clocked Synchronous Mode) .................................... 395
15.6.4 Serial Data Reception (Clocked Synchronous Mode).......................................... 398
15.6.5 Simultaneous Serial Data Transmission and Reception
(Clocked Synchronous Mode) ............................................................................. 400
15.7 IrDA Operation ................................................................................................................. 402
15.8 Interrupt Sources............................................................................................................... 405
15.9 Usage Notes ...................................................................................................................... 406
15.9.1 Module Stop Mode Setting.................................................................................. 406
15.9.2 Break Detection and Processing .......................................................................... 406
15.9.3 Mark State and Break Detection.......................................................................... 406
15.9.4 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only) .................................................................... 406
15.9.5 Relation between Writing to TDR and TDRE Flag............................................. 406
15.9.6 Restrictions on Using DTC.................................................................................. 407
15.9.7 SCI Operations during Mode Transitions ............................................................ 407
15.9.8 Notes on Switching from SCK Pins to Port Pins ................................................. 411
Section 16 I
2
C Bus Interface (IIC) (Optional)............................................................. 413
16.1 Features............................................................................................................................. 413
16.2 Input/Output Pins.............................................................................................................. 416
16.3 Register Descriptions........................................................................................................ 417
16.3.1 I
2
C Bus Data Register (ICDR) ............................................................................. 417
16.3.2 Slave Address Register (SAR)............................................................................. 418
16.3.3 Second Slave Address Register (SARX) ............................................................. 419
16.3.4 I
2
C Bus Mode Register (ICMR)........................................................................... 421
16.3.5 I
2
C Bus Control Register (ICCR)......................................................................... 424
16.3.6 I
2
C Bus Status Register (ICSR)............................................................................ 431
16.3.7 DDC Switch Register (DDCSWR)...................................................................... 436
16.3.8 I
2
C Bus Extended Control Register (ICXR)......................................................... 438
16.4 Operation .......................................................................................................................... 442
16.4.1 I
2
C Bus Data Format ............................................................................................ 442
16.4.2 Initialization......................................................................................................... 444
16.4.3 Master Transmit Operation.................................................................................. 444
16.4.4 Master Receive Operation.................................................................................... 448
16.4.5 Slave Receive Operation...................................................................................... 457
16.4.6 Slave Transmit Operation .................................................................................... 465
16.4.7 IRIC Setting Timing and SCL Control ................................................................ 468
16.4.8 Automatic Switching from Formatless Mode to I
2
C Bus Format ........................ 470
16.4.9 Operation Using DTC.......................................................................................... 471
16.4.10 Noise Canceler..................................................................................................... 472