Datasheet

Section 2 CPU
Rev. 3.00 Mar 21, 2006 page 58 of 788
REJ09B0300-0300
End of bus request
Bus request
Program execution
state
Bus-released state
Sleep mode
Exception-handling state
Software standby mode
RES = high
Reset state
*
1
STBY = high, RES = low
Hardware standby mode
*
2
Power-down state
*
3
Notes: 1.
2.
3.
From any state except hardware standby mode, a transition to the reset state occurs whenever RES
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
From any state, a transition to hardware standby mode occurs when STBY goes low.
The power-down state also includes watch mode, subactive mode, subsleep mode, etc. For details,
refer to section 26, Power-Down Modes.
SLEEP
instruction
with
LSON = 0,
SSBY = 0
Interrupt
request
End of bus
request
Bus
request
Request for
exception
handling
End of
exception
handling
External interrupt
request
SLEEP
instruction
with
LSON = 0,
PSS = 0,
SSBY = 1
Figure 2.13 State Transitions