Datasheet

Section 2 CPU
Rev. 3.00 Mar 21, 2006 page 40 of 788
REJ09B0300-0300
2.6 Instruction Set
The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as
shown in table 2.1.
Table 2.1 Instruction Classification
Function Instructions Size Types
MOV B/W/L
POP
*
1
, PUSH
*
1
W/L
LDM
*
5
, STM
*
5
L
Data transfer
MOVFPE
*
3
, MOVTPE
*
3
B
5
ADD, SUB, CMP, NEG B/W/L
ADDX, SUBX, DAA, DAS B
INC, DEC B/W/L
ADDS, SUBS L
MULXU, DIVXU, MULXS, DIVXS B/W
EXTU, EXTS W/L
Arithmetic operations
TAS
*
4
B
19
Logic operations AND, OR, XOR, NOT B/W/L 4
Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,
ROTXR
B/W/L 8
Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST,
BAND, BIAND, BOR, BIOR, BXOR, BIXOR
B14
Branch Bcc
*
2
, JMP, BSR, JSR, RTS — 5
System control
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,
NOP
— 9
Block data transfer EEPMOV — 1
Total: 65
Legend: B: Byte size
W: Word size
L: Longword size.
Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,
@–SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L
ERn, @–SP.
2. Bcc is the general name for conditional branch instructions.
3. Cannot be used in this LSI.
4. When using the TAS instruction, use registers ER0, ER1, ER4, and ER5.
5. ER7 is not used as the register that can be saved (STM)/restored (LDM) when using
STM/LDM instruction, because ER7 is the stack pointer.