Datasheet

Appendix A I/O Port States in Each Processing State
Rev. 3.00 Mar 21, 2006 page 778 of 788
REJ09B0300-0300
Port Name
Pin Name
MCU Operating
Mode Reset
Hardware
Standby
Mode
Software
Standby
Mode
Watch
Mode
Sleep
Mode
Sub-
sleep
Mode
Subactive
Mode
Program
Execution
State
1 Clock
output
2, 3 (EXPE = 1)
Port 96
φ
EXCL
2, 3 (EXPE = 0)
T
T [DDR = 1] H
[DDR = 0] T
EXCL
input
[DDR = 1]
clock
output
[DDR = 0] T
EXCL
input
EXCL input Clock output/
EXCL input/
input port
1H
2, 3 (EXPE = 1)
HHHHAS, HWR,
RD
AS, HWR,
RD
Ports 95 to 93
AS, HWR, RD
2, 3 (EXPE = 0)
T
T
kept kept kept kept I/O port I/O port
1
2, 3 (EXPE = 1)
Ports 92, 91
2, 3 (EXPE = 0)
T T kept kept kept kept I/O port I/O port
1
2, 3 (EXPE = 1)
H/kept H/kept H/kept H/kept LWR/
I/O port
LWR/
I/O port
Port 90
LWR
2, 3 (EXPE = 0)
TT
kept kept kept kept I/O port I/O port
1 I/O port I/O port
2, 3 (EXPE = 1) A23 to A16/
I/O port
A23 to A16/
I/O port
Port A
A23 to A16
2, 3 (EXPE = 0)
TT kept
*
kept
*
kept
*
kept
*
I/O port I/O port
1
2, 3 (EXPE = 1)
T/kept T/kept T/kept T/kept D7 to D0/
I/O port
D7 to D0/
I/O port
Port B
D7 to D0
2, 3 (EXPE = 0)
TT
kept kept kept kept I/O port I/O port
1
2, 3 (EXPE = 1)
Ports C to G
(H8S/2160B,
H8S/2161B)
2, 3 (EXPE = 0)
T T kept kept kept kept I/O port I/O port
Legend:
H: High
L: Low
T: High-impedance state
kept: Input ports are in the high-impedance state (when DDR = 0 and PCR = 1, input pull-up
MOSs remain on).
Output ports maintain their previous state.
Depending on the pins, the on-chip peripheral modules may be initialized and the I/O port
function determined by DDR and DR used.
DDR: Data direction register
Note: * In the case of address output, the last address accessed is retained.