Datasheet

Section 27 Electrical Characteristics
Rev. 3.00 Mar 21, 2006 page 752 of 788
REJ09B0300-0300
Condition
A
Condition
B
Condition
C
10 MHz 16 MHz 20 MHz
Item Symbol Min Max Min Max Min Max Unit
Test
Conditions
Single edge t
TMCWH
1.5 — 1.5 — 1.5 —TMR Timer
clock
pulse
width
Both edges t
TMCWL
2.5 — 2.5 — 2.5 —
t
cyc
Figure 27.20
PWM,
PWMX
Pulse output delay time t
PWOD
— 100 — 50 — 50 ns Figure 27.22
Asynchronous t
Scyc
4 — 4 — 4 —Input
clock
cycle
Synchronous
6 — 6 — 6 —
t
cyc
Input clock pulse width t
SCKW
0.4 0.6 0.4 0.6 0.4 0.6 t
Scyc
Input clock rise time t
SCKr
— 1.5 — 1.5 — 1.5
Input clock fall time t
SCKf
— 1.5 — 1.5 — 1.5
t
cyc
Figure 27.23
Transmit data delay time
(clocked synchronous)
t
TXD
— 100
— 50 — 50
Receive data setup time
(clocked synchronous)
t
RXS
100 — 50 — 50 —
SCI
Receive data hold time
(clocked synchronous)
t
RXH
100 — 50 — 50 —
ns
Figure 27.24
A/D
converter
Trigger input setup time t
TRGS
50 — 30 — 30 — ns Figure 27.25
RESO output delay time t
RESD
— 200 — 120 — 100 nsWDT
RESO output pulse width t
RESOW
132 —
132 — 132 — t
cyc
Figure 27.26
Note: * Only peripheral modules that can be used in subclock operation