Datasheet

Section 27 Electrical Characteristics
Rev. 3.00 Mar 21, 2006 page 745 of 788
REJ09B0300-0300
27.2.3 AC Characteristics
The following shows the clock timing, control signal timing, bus timing, and on-chip peripheral
function timing. For the AC characteristics test conditions, see figure 27.3.
Clock Timing: Table 27.20 shows the clock timing. The clock timing specified here covers clock
(φ) output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation
settling times. For details of external clock input (EXTAL pin and EXCL pin) timing, see section
25, Clock Pulse Generator.
Table 27.20 Clock Timing
Condition A: V
CC
= 5.0 V ±10%, V
CC
B = 5.0 V ±10%, V
SS
= 0 V, φ = 2 MHz to maximum
operating frequency, T
a
= –20 to +75°C (normal specification product),
T
a
= –40 to +85°C (wide range temperature specification product)
Condition B: V
CC
= 4.0 V to 5.5 V, V
CC
B = 4.0 V to 5.5 V, V
SS
= 0 V, φ = 2 MHz to maximum
operating frequency, T
a
= –20 to +75°C (normal specification product),
T
a
= –40 to +85°C (wide range temperature specification product)
Condition C: V
CC
= 2.7 V to 3.6 V, V
CC
B = 2.7 V to 5.5 V, V
SS
= 0 V, φ = 2 MHz to maximum
operating frequency, T
a
= –20 to +75°C
Condition A Condition B Condition C
10 MHz 16 MHz 20 MHz
Item Symbol Min Max Min Max Min Max Unit
Test
Conditions
Clock cycle time t
cyc
100 500 62.5 500 50 500 ns Figure 27.6
Clock high pulse width t
CH
30 — 20 — 17 — ns
Clock low pulse width t
CL
30 — 20 — 17 — ns
Clock rise time t
Cr
— 20 — 10 — 8ns
Clock fall time t
Cf
— 20 — 10 — 8ns
Figure 27.6
Oscillation settling
time at reset (crystal)
t
OSC1
20 — 10 — 10 — ms Figure 27.7
Oscillation settling
time in software
standby (crystal)
t
OSC2
8 — 8 — 8 — ms
External clock output
stabilization delay time
t
DEXT
500 — 500 — 500 — µs
Figure 27.8