Datasheet

Section 27 Electrical Characteristics
Rev. 3.00 Mar 21, 2006 page 716 of 788
REJ09B0300-0300
Condition
10 MHz
Item Symbol Min Max Unit Test Conditions
Transmit data delay time
(synchronous)
t
TXD
— 100 ns
Receive data setup time
(synchronous)
t
RXS
100 — ns
SCI
Receive data hold time
(synchronous)
t
RXH
100 — ns
Figure 27.24
A/D
converter
Trigger input setup time t
TRGS
50 — ns Figure 27.25
RESO output delay time t
RESD
— 200 nsWDT
RESO output pulse width t
RESOW
132 — t
cyc
Figure 27.26
Note: * Only peripheral modules that can be used in subclock operation
Table 27.8 Timing of On-Chip Peripheral Modules (2)
Condition: V
CC
= 2.7 V to 3.6 V, V
CC
B = 2.7 V to 5.5 V, V
SS
= 0 V, φ = 2 MHz to maximum
operating frequency, T
a
= –20 to +75°C
Condition
10 MHz
Item Symbol Min Max Unit Test Conditions
CS/HA0 setup time t
HAR
10 — ns
CS/HA0 hold time t
HRA
10 — ns
IOR pulse width t
HRPW
220 — ns
HDB delay time t
HRD
— 200 ns
HDB hold time t
HRF
040ns
XBS read
cycle
HIRQ delay time t
HIRQ
— 200 ns
CS/HA0 setup time t
HAW
10 — ns
CS/HA0 hold time t
HWA
10 — ns
IOW pulse width t
HWPW
100 — ns
Fast A20 gate not
used
50 — nsHDB setup
time
Fast A20 gate
used
t
HDW
85 — ns
HDB hold time t
HWD
25 — ns
XBS write
cycle
GA20 delay time t
HGA
— 180 ns
Figure 27.27