Datasheet

Section 1 Overview
Rev. 3.00 Mar 21, 2006 page 21 of 788
REJ09B0300-0300
Pin No.
Type Symbol
FP-100B,
TFP-100B
TFP-144 I/O Name and Function
PS2AC
PS2BC
PS2CC
31
21
11
39
37
34
Input/
Output
Keyboard buffer controller
synchronization clock input/output pins.
Keyboard
buffer
controller
PS2AD
PS2BD
PS2CD
30
20
10
38
35
33
Input/
Output
Keyboard buffer controller data
input/output pins.
HDB7 to
HDB0
89 to 82 128 to
121
Input/
Output
Bidirectional 8-bit bus for accessing
XBS.
CS1,
CS2/
ECS2,
CS3, CS4
18, 94,
25, 81, 80
19, 130,
24, 118,
117
Input Input pins for selecting XBS channels 1
to 4. The CS2 or ECS2 input pin is
selected with the system control
register.
IOR 22 21 Input Input pin that enables reading from
XBS.
IOW 19 20 Input Input pin that enables writing to XBS.
HA0 93 129 Input Input pin that indicates whether an
access is a data access or command
access.
GA20 94 130 Output A20 gate control signal output pin.
HIRQ11
HIRQ1
HIRQ12
HIRQ3
HIRQ4
52
53
54
91
90
2
3
4
120
119
Output Output pins for interrupt requests to the
host.
Host
interface
(XBS)
HIFSD 95 131 Input Control input pin used to place XBS
input/output pins in the high-impedance/
cutoff state.
LAD3 to
LAD0
85 to 82 124 to
121
Input/
Output
LPC command, address, and data
input/output pins.
Host
interface
(LPC)
LFRAME 86 125 Input Input pin that indicates the start of an
LPC cycle or forced termination of an
abnormal LPC cycle.
LRESET 87 126 Input Input pin that indicates an LPC reset.
LCLK 88 127 Input The LPC clock input pin.