Datasheet

Section 25 Power-Down Modes
Rev. 3.00 Mar 21, 2006 page 646 of 788
REJ09B0300-0300
• MSTPCRL
Bit Bit Name Initial Value R/W Corresponding Module
7 MSTP7 1 R/W Serial communication interface_0 (SCI_0)
6 MSTP6 1 R/W Serial communication interface_1 (SCI_1)
5 MSTP5 1 R/W Serial communication interface_2 (SCI_2)
4 MSTP4 1 R/W I
2
C bus interface_0 (IIC_0)
3 MSTP3 1 R/W I
2
C bus interface_1 (IIC_1)
2 MSTP2 1 R/W Host interface (XBS), keyboard buffer controller,
keyboard matrix interrupt mask register (KMIMR),
keyboard matrix interrupt mask register A (KMIMRA),
port 6 pull-up MOS control register (KMPCR)
1 MSTP1 1
*
R/W 
0 MSTP0 1 R/W Host interface (LPC), wake-up event interrupt mask
register B (WUEMRB)
Note: * This bit can be read from or written to, however, operation is not affected.
25.2 Mode Transitions and LSI States
Figure 25.1 shows the enabled mode transition diagram. The mode transition from program
execution state to program halt state is performed by the SLEEP instruction. The mode transition
from program halt state to program execution state is performed by an interrupt. The STBY input
causes a mode transition from any state to hardware standby mode. The RES input causes a mode
transition from a state other than hardware standby mode to the reset state. Table 25.2 shows the
LSI internal states in each operating mode.