Datasheet

Section 24 Clock Pulse Generator
Rev. 3.00 Mar 21, 2006 page 638 of 788
REJ09B0300-0300
24.4 Bus Master Clock Select Circuit
The bus master clock select circuit selects a clock to supply the bus master with either the system
clock (φ) or medium-speed clock (φ/2, φ/4, φ/8, φ/16, or φ/32) by the SCK2 to SCK0 bits in
SBYCR.
24.5 Subclock Input Circuit
The subclock input circuit controls subclock input from the EXCL pin.
Inputting the Subclock: To use the subclock, a 32.768-kHz external clock should be input from
the EXCL pin. At this time, the P96DDR bit in P9DDR should be cleared to 0, and the EXCLE bit
in LPWRCR should be set to 1.
Subclock input conditions are shown in table 24.5. When the subclock is not used, subclock input
should not be enabled.
Table 24.5 Subclock Input Conditions
Vcc = 2.7 to 5.5 V
Item Symbol Min Typ Max Unit
Measurement
Condition
Subclock input pulse width
low level
t
EXCLL
— 15.26 — µs
Subclock input pulse width
high level
t
EXCLH
— 15.26 — µs
Subclock input rising time t
EXCLr
——10 ns
Subclock input falling time t
EXCLf
——10 ns
Figure 24.7
t
EXCLH
t
EXCLL
t
EXCLr
t
EXCLf
V
CC
× 0.5
EXCL
Figure 24.7 Subclock Input Timing