Datasheet

Section 23 ROM
Rev. 3.00 Mar 21, 2006 page 617 of 788
REJ09B0300-0300
23.6 Operating Modes
The flash memory is connected to the CPU via a 16-bit data bus, enabling byte data and word data
to be accessed in a single state. Even addresses are connected to the upper 8 bits and odd addresses
are connected to the lower 8 bits. Note that word data must start from an even address.
On-chip ROM is enabled or disabled by the mode select pins (MD1 and MD0) and the EXPE bit
in MDCR, as summarized in table 23.3.
In normal mode (mode 3), up to 56 kbytes of ROM can be used.
Table 23.3 Operating Modes and ROM
Operating Modes Mode Pins MDCR
MCU
Operating
Mode
CPU
Operating
Mode
Mode MD1 MD0 EXPE
On-Chip
ROM
Mode 1 Normal Expanded mode with
on-chip ROM disabled
0 1 1 Disabled
Advanced Single-chip mode 1 0 0Mode 2
Advanced Expanded mode with
on-chip ROM enabled
10 1
Enabled
(64/128/25
6 kbytes)
Normal Single-chip mode 1 1 0Mode 3
Normal Expanded mode with
on-chip ROM enabled
11 1
Enabled
(56 kbytes)
23.7 On-Board Programming Modes
An on-board programming mode is used to perform on-chip flash memory programming, erasing,
and verification. This LSI has two on-board programming modes: boot mode and user program
mode. Table 23.4 shows pin settings for boot mode. In user program mode, operation by software
is enabled by setting control bits. For details on flash memory mode transitions, see figure 23.2.