Datasheet

Section 21 A/D Converter
Rev. 3.00 Mar 21, 2006 page 595 of 788
REJ09B0300-0300
Table 21.3 A/D Conversion Time (Single Mode)
CKS = 0 CKS = 1
Item Symbol min typ max min typ max
A/D conversion start delay time t
D
10 — 17 6 — 9
Input sampling time t
SPL
— 63 ——31 —
A/D conversion time t
CONV
259 — 266 131 — 134
Note: * Values in the table indicate the number of states.
21.4.4 External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to B’11 in
ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets
the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as when the ADST bit has been set to 1 by software. Figure 21.4 shows the
timing.
φ
ADTRG
Internal trigger
signal
ADST
A/D conversion
Figure 21.4 External Trigger Input Timing