Datasheet

Section 21 A/D Converter
Rev. 3.00 Mar 21, 2006 page 594 of 788
REJ09B0300-0300
21.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
D
) passes after the ADST bit in ADCSR is set to
1, then starts A/D conversion. Figure 21.3 shows the A/D conversion timing. Table 21.3 indicates
the A/D conversion time.
As indicated in figure 21.3, the A/D conversion time (t
CONV
) includes t
D
and the input sampling time
(t
SPL
). The length of t
D
varies depending on the timing of the write access to ADCSR. The total
conversion time therefore varies within the ranges indicated in table 21.3.
In scan mode, the values given in table 21.3 apply to the first conversion time. In the second and
subsequent conversions, the conversion time is 256 state (fixed) when CKS = 0 and 128 states
(fixed) when CKS = 1.
φ
Address
Write signal
Input sampling
timing
ADF
Legend:
(1) : ADCSR write cycle
(2) : ADCSR address
t
D
: A/D conversion start delay
t
SPL
: Input sampling time
t
CONV
: A/D conversion time
(1)
(2)
t
D
t
SPL
t
CONV
Figure 21.3 A/D Conversion Timing