Datasheet

Section 19 Host Interface LPC Interface (LPC)
Rev. 3.00 Mar 21, 2006 page 541 of 788
REJ09B0300-0300
R/W
Bit Bit Name Initial Value Slave Host Description
5 SDWN 0 R/(W)
*
— LPC Shutdown Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when an LPC hardware shutdown request is
generated.
0: [Clearing conditions]
• Writing 0 after reading SDWN = 1
• LPC hardware reset and LPC software reset
1: [Setting condition]
LPCPD pin falling edge detection
4 ABRT 0 R/(W)
*
— LPC Abort Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when a forced termination (abort) of an LPC transfer
cycle occurs.
0: [Clearing conditions]
• Writing 0 after reading ABRT = 1
• LPC hardware reset and LPC software reset
• LPC hardware shutdown and LPC software
shutdown
1: [Setting condition]
LFRAME pin falling edge detection during LPC
transfer cycle
3IBFIE30 R/W— IDR3 and TWR Receive Completion Interrupt
Enable
Enables or disables IBFI3 interrupt to the slave
processor (this LSI).
0: Input data register IDR3 and TWR receive
completed interrupt requests disabled
1: [When TWRIE = 0 in LADR3]
Input data register (IDR3) receive completed
interrupt requests enabled
[When TWRIE = 1 in LADR3]
Input data register (IDR3) and TWR receive
completed interrupt requests enabled